Bit error measurement system

ABSTRACT

A bit error measurement system provides means for generating test patterns, multiplexing means and means for specifying and recording a pattern position. In a first aspect, a bit error measurement system has a pattern generator having M channels of pattern generation and a pattern generation controller 10 for controlling the pattern generation in the M channels so that when one channel is selected to generate a pattern the other channels are controlled to be waiting. In a second aspect, a clock frequency difference detector 150 is provided for counting a frequency of an input clock 111 and comparing the results with the frequency at the time of previous switching to detect whether the frequency change is greater than a predetermined value to judge whether the system is in a measurement state and to permit or prohibit a switching operation of a clock switch circuit. In a third aspect, a pattern position recording part 210 is provided to store pattern position information of a reference pattern generator 262 when an error detection signal 265 a  is received from a comparator 265.

TECHNICAL FIELD

This invention relates to a bit error measurement system for testing abit error rate, and more particularly, firstly, to a bit errormeasurement system which has a bit error test pattern generator and abit error measurement apparatus for analyzing bit error rates of anoutput signal from a device under test by interchangeably switchingbetween specific patterns and random patterns in real time. Secondly,this invention relates to a bit error test pattern generator whichautomatically switches clock edges of a multiplexing clock signal to beused for generating a high speed pattern by sequentially multiplexingparallel patterns generated by a pattern generator. Thirdly, thisinvention relates to a bit error measurement system which is able tospecify and record positions of the pattern that involved in bit errors.

BACKGROUND ART

A first example of a conventional technology is show in the following.

Namely, a bit error test pattern generator/bit error measurementapparatus in the conventional technology is described below in which atest pattern is generated by interchanging specific patterns and randompattern in real time to analyze bit errors in the output signal from adevice under test.

In a bit error measurement system, a test pattern of test speed up toseveral 10 GHz is applied to a device under test DUT, and performance ofthe DUT is analyzed by measuring a bit error rate while changing thetest conditions.

In the conventional bit error measurement system, a test pattern to begiven to the DUT is generated in either one of the two forms. One is apseudo random binary sequence (PRBS) pattern generation and the other isa word pattern generation in which contents of a memory are repeatedlygenerated. This test pattern is supplied to the DUT, and the resultantoutputs of the DUT is compared with expected pattern signals. The numberof bit errors is counted and an error rate is calculated and displayed.

FIG. 5 shows an example of a test arrangement for a bit errormeasurement system. A test pattern signal 71_(pat) and a clock signal 73from a pattern generator 71 are provided to a DUT 74. The resultantoutput from the DUT 74 which is a signal 61 to be measured and a clocksignal 60 are provided to a bit error measurement apparatus 75 whereby abit error is measured.

FIG. 6 shows an internal structure of the pattern generator 71. Forgenerating a test pattern to be supplied to the DUT 74, the patterngenerator 71 includes a PRBS generator 71_(prbs) which generates a PRBS(pseudo random binary sequence) pattern, and a WORD generator 71_(word)which generates a word pattern based on the contents of a memory. Eitherone of the patterns is fixedly selected by a multiplexer (MUX) 71_(m)and is provided with a desired amplitude and offset voltage by a bufferamplifier 71_(buf). Then the test pattern is applied to the DUT 74. Thecontents of the memory and other conditions for the pattern generationare set in advance through an external CPU (computer) to satisfy thedesired test conditions.

In receiving the test pattern signal, the DUT shown in FIG. 5 outputspattern data, which for example, may be the same data received as inputdata, to the bit error measurement apparatus 75. The bit errormeasurement apparatus 75 receives the output data from the DUT 74 andcompares the data with expected pattern internally generated and countsthe number of bits which do not match with one another, calculates a biterror rate, and displays the results.

FIG. 7 shows an internal structure of the bit error measurementapparatus 75. The received signal 61 that is to be measured is compared,by a comparator 65, with a reference pattern from a reference patterngenerator 62. The number of bits which do not match with one another arecounted by an error counter 70.

Since the position of the pattern sequence in the received signal 61 tobe tested from the DUT 74 and the position of the bit sequence from thereference pattern generator 62 are undefined, the measurement apparatusincludes a pattern synchronization part 66 for synchronizing patternpositions of both of the bit sequence. A synchronization detectioncounter 66_(a) in the pattern synchronization part 66 is to detectwhether the error rate is less than a predetermined value. For example,the synchronization detection counter 66_(a) counts the number ofmismatch bits 65_(err) for a fixed clock time period (for example, for aperiod of 16,384 clock pulses). A comparison test pulse 66_(tst) isgiven to a comparator 66_(c) whereby the counted number of mismatch anda threshold value are compared. At the same time, the synchronizationdetection counter 66_(a) is reset to an initial value to repeat theabove detection procedure.

If the results of the comparison is greater than the threshold valuefrom a threshold value register 66_(b), it is considered that theposition of the both bit sequence is still not aligned. Thus, a clockmask signal 67 is provided to the reference pattern generator 62 tosuspend the pattern generation for one clock time so as to shift the bitsequence.

This operation for the pattern synchronization detection is repeated forevery fixed clock period while shifting the bit sequence by one clocktime until the pattern sequence coincide with each other. When thecoincidence in the pattern sequence is detected, it is deemed that bothof the patterns are synchronized and thus the operation for thesynchronization detection is finished and an actual bit errormeasurement is undertaken.

With respect to the internal structure of the reference patterngenerator 62, the two generators, the PRBS generator 62_(prbs) and theword generator 62_(word) are identical to the generators in the testpattern generator 71 except for the clock mask function where thepattern is shifted by one clock time as noted above. The same type ofthe pattern generator now used in the pattern generator 71 is set in thereference pattern generator to generate the reference pattern 62_(pat)which is supplied to the comparator 65.

The above noted various data in the measurement system, thesynchronization conditions, the measurement conditions and the like areset in advance through an external CPU to meet the desired testrequirements.

The second example of the conventional technology is described below.

This example relates to a bit error measurement system of theconventional technology which produces a high speed test pattern bysequentially multiplexing parallel patterns generated by a patterngenerator. In this bit error measurement system, edges of a clock signalfor multiplexing the patterns are automatically switched.

FIG. 11 shows a configuration of this wide band pulse pattern generator.The pulse pattern generator is mainly used to measure a bit error rateof a device under test (DUT) by providing the pulse pattern to the DUT.

The pattern generator is formed of a pattern generation circuit 113,multiplexing circuits 114₁ -114_(n), an intermediate retiming circuit127, 1/2 divider circuits 112₁ -112_(n), delay circuits 115₁ -115_(n)and 115_(r), a clock switching circuit 128, and an approach detectioncircuit 131.

An input clock 111 is an externally given clock signal having unknownclock rates. The frequency of the input clock 111 extends in a widerange, for example from 50 MHz to 10 GHz which is freely set by a userin advance. However, the clock rate of the clock 111 must be constantwhen measuring the bit error of the DUT.

Since it is necessary to correctly multiplex and retime the patterns forany clock rates of this wide range input clock 111, the patterngenerator includes the delay circuits 115₁ -115_(n) for providing delaytimes (τ₀, τ₀ +τ₁, τ₀ +τ₁ +τ₂,,, τ₀ +τ₁ +,,+τ_(m-1), τ_(m),τ_(m+),,+τ_(n-1), τ_(m+),,+τ_(n)) to the clock signal equivalent to thedelay times caused by propagation delays in the circuit components andwiring between the pattern generation circuit 113 and multiplexingcircuits. In such a circuit arrangement, in the past, it is necessaryfor the delay circuits to have longer delay times in the later stages.Further, high quality clock with less jitters is required since thepattern generator operates in high speed. However, the circuit of FIG.11 alleviates this requirements by having the intermediate retimingcircuit 127, the clock switching circuit 128, and the approach detectioncircuit 131 to cancel the delay times (τ₀ +τ₁ +,,+τ_(m-1)) in the priorstages.

The brief explanation is given in the following regarding the operationsconcerning the intermediate retiming circuit 127, the clock switchingcircuit 128, and the approach detection circuit 131. The more detaileddescription is shown in Japanese patent application Ser. No.218454-1990.

The approach detection circuit 131 is formed of a coincidence circuit132, an average circuit 133, a comparator 134 and a T-type flip-flop135.

It is stated in the Japanese patent application Ser. No. 218454-1990that when a retiming clock for the intermediate retiming circuit 127approaches too close to a transition point of the input pattern to theretiming circuit 127, a correct retiming will not be available. Thus,the Japanese patent application states, that when the retiming clock andthe pattern transition point are too close with each other, thatsituation is detected by the approach detection circuit 131. Based onthe detection signal, a phase of the clock, which is provided to thedivider circuits to control the multiplexing operation, is switched. Asa result, the delay times (τ₀ +τ₁ +,,+τ_(m-1)) in the prior stages arecanceled by the foregoing operation.

When adjusting the clock rate conditions, the clock switching circuit128 switches to a clock phase which is more stably retiming thepatterns. During the measurement, the input clock rate must be constant,and thus the clock switching must not be taken place. This is because ifthe clock switching operation is taken place, it is not possible to testthe bit error.

The third example of the conventional technology is described in thefollowing.

This example relates to a bit error measurement system of conventionaltechnology which specifies and records a position of a pattern where abit error is produced.

FIG. 17 shows an example of test arrangements in which a bit errormeasurement system is used. For testing a device 274, a test patternsignal 272 and a clock signal 273 from a pattern generator 271 areprovided to the device under test 274. The resultant output from thedevice under test 274 which is a signal 261 to be measured and a clocksignal 260 are provided to a bit error measurement apparatus 275 wherebya bit error is measured. In this situation, it is necessary to measurethe bit error by setting the test pattern 272 and a reference patterngenerated by the bit error measurement apparatus 275 identical with oneanother.

When the test speed is extremely high, 10 GHz for example, the deviceunder test 274 may generate an abnormal serial pattern at the timingwhen the operation of the device under test is unstable. The bit errormeasurement system analyzes such pattern conditions that have caused thebit error.

Here, a serial process of the bit error measurement is shown in thefollowing.

FIG. 18(a) is a block diagram of a conventional bit error measurementapparatus for explaining the process of bit error measurement. The biterror measurement apparatus is formed of a reference pattern generator262, a comparator 265, an error counter 270, a pattern synchronizationpart 266. The pattern synchronization part 266 is provided forsynchronizing patterns between the signal 261 to be measured and thereference pattern generator 262. The pattern synchronization part 266 isformed of a synchronization detection counter 266_(a), a threshold valueregister 266_(b) and a comparator 266_(c).

The pattern synchronization within in this context means that even ifbit errors exist to a certain extent in the unknown signal 261 to bemeasured, synchronization is deemed to be established. In other words,if the error rate is lower than a certain level such as shown in thethreshold register 266_(b), it is deemed to be synchronized. Thesynchronization detection counter 266_(a) is a counter which counts thenumber of bit errors for every predetermined time period. After thepredetermined time period, the counted value and the data from thethreshold register 266_(b) are compared by the comparator 266_(c). Whenthe comparator 266_(c) detects that the number of bit errors is lessthan the threshold value, a clock mask signal 267 is no longer generatedtherefrom.

The reference pattern generator 262, when receiving the clock masksignal 267, delays the output phase of the reference pattern signal262_(a) by one bit to generate the next reference pattern. This processis continued consecutively until the reference pattern 262a matches withthe input signal 261 to be measured. When the reference pattern 262_(a)matches with the input signal, the clock mask signal 267 from thecomparator 266_(c) is no longer generated, and thus, the referencepattern 262_(a) is maintained in the synchronized situation. In thismanner, a pattern synchronization is established between the signal 261to be measured and the reference pattern generator 262.

Thereafter, under this synchronization situation, the real bit errormeasurement is carried out.

The comparator 265 compares the signal under test 261 for every bit, anddetects the resultant bit errors. The error counter 270 counts up thebit errors. The counted value is read by the CPU at every predeterminedtime period to calculate the error rate, and the number of errors willbe output, for example, by means of a display.

Here, a parallel process of the bit error measurement is shown in thefollowing.

FIG. 18(b) is a block diagram showing an example of a conventional biterror measurement apparatus for a parallel process. In this case, anultra high speed signal 261 to be measured is converted to a low speedparallel signal before the measurement. The bit error measurementapparatus is formed of a demultiplexes (DEMUX) 264, a reference patterngenerator 262, a divider 263, a comparator 265, an error counter 270 anda pattern synchronization part 266.

As in the foregoing explanation, the pattern synchronization part 266generates a clock mask signal when the synchronization state is notreached. The divider 263, in receiving the clock mask signal, suspends adivided clock 263_(a) by one bit. The DEMUX 264 receives the dividedclock 263_(a), and will not fetch the input signal to be measured whenthe divided clock 263_(a) is suspended. The reference pattern generatormaintains the reference pattern 262_(a) when the divided clock 263_(a)is suspended. Therefore, a phase difference between a signal under testat the comparator 265 which is an output signal 264_(a) of the DEMUX andthe reference pattern signal 262_(a) shifts corresponding to the time(one bit) during which the divided clock 263_(a) is suspended. Therelationship between the DEMUX output 264_(a) and the reference patternsignal 262_(a) in this situation is shown in FIG. 19.

By repeating this process, the synchronization is established.

After reaching the synchronization, the real bit error measurement isinitiated. Since this example operates in a 16-bit parallel manner, theerror counter 270 is formed of 16 counters each of which corresponds toone of the 16 bits. The CPU reads the number of errors in the 16counters and adds the results to display the same.

Three problems exist in the conventional technology in the above to besolved by the present invention, which are as follows:

First, as shown in the bit error measurement system which can specifythe pattern position which caused the bit errors, the conventional biterror measurement system selects and generates either one of the wordpattern generator or the PRBS pattern generator. Although the PRBSpattern generator can generate a long period pattern, it is not able togenerate a specified bit sequence. On the other hand, although the wordpattern generator can generate a desired bit sequence, it is not able togenerate a long period pattern since there is a limit in the capacity ofthe memory.

As a consequence, it is not possible to fully test communication devicesby generating a mixed test pattern of a long period and pseudo randompattern which is similar to transmission frames (such as STM, SDH, ATM)in an actual communication network. Thus, the conventional bit errormeasurement system is not appropriate for evaluating this type ofcommunication devices.

Second, as noted above, in the conventional bit error measurement systemwhich includes the bit error pattern generator which is able toautomatically switch clock edges of the clock signal to sequentiallymultiplex the parallel patterns to form the high speed test pattern, theapproach detection circuit 131 is constantly in operation even when thesystem is in the bit error measurement process. This means that theapproach detection circuit 131 detects such an approach between theretiming clock and the pattern transition point which is caused by minorchanges in the clock rate of the input clock which is produced bytemperatures changes and the like. In such a situation of the clock ratechanges, in most cases, the multiplexing operation of the patterns isperformed properly. Nevertheless, the clock phase is switched in such asituation in the conventional technology.

This clock switch causes the bit stream of the output test pattern aninstant indeterminate state. This indeterminate state in the patternincreases unstable parameters in the bit error measurement and mayadversely affect the measurement, which is not proper to fully use themeasurement system.

Third, as noted above with respect to the bit error measurement systemwhich specifies and records the position of the test pattern whichcaused the bit errors, the error information acquired by the errorcounter 270 is not enough to fully analyze and specify the real cause ofthe error in the signal under test. To do this, in the conventionaltechnology, the contents of the test pattern, i.e., the contents in thepattern generator 271 and the reference pattern generator 262 have beenchanged in various manners to see corresponding changes in the biterrors, such as increase or decrease. In this manner, the causes of thebit errors such as pattern conditions, pattern categories areidentified.

As has been foregoing, the error counter 270 is sufficient to find thebit errors but is not sufficient to fully analyze and specify thepattern conditions which caused the bit errors, which is inconvenient inthe use of the bit error measurement system.

Therefore, there are three objects of the present invention as follow.First, it is an object of the present invention to provide a bit errormeasurement system which is capable of multiplexing and generatingspecified bit sequence patterns and long period random patterns so thatthe bit error measurement is available based on this test patterns.Second, it is an object of the present invention to provide a bit errormeasurement system which is capable of allowing or inhibiting theoperation of the clock switch circuit 128 based on whether themeasurement system is in the measurement process or not by monitoringthe clock rate of the clock 111. Thus, it is able to provide a stable,wide band pulse pattern generator which can suppress the unstableoperation based on the clock switching. Third, it is an object of thepresent invention to provide a bit error measurement system whichfacilitates the error analysis for the bit errors by recording theaddress information of the reference pattern generator 262 so as toidentify the position of the reference pattern in which the bit error isdetected. Thus, the pattern position which produced the bit errors areeasily identified and thus the error analysis for finding the cause ofthe error is performed more easily.

DISCLOSURE OF THE INVENTION

The solution of the above noted problems in accordance with the firstinvention is described below.

This invention includes a bit error test pattern generator/bit errormeasurement apparatus which is able to switch between specific patternsand random patterns in real time and analyze the bit errors in theoutput signal from the device under test.

FIG. 1 is a block diagram showing a first solution by the firstinvention.

To solve the above noted problems, the first invention includes apattern generator having M channels of pattern generation. The channelsof pattern generation are sequentially switched in real time. A patterngeneration controller 10 is provided to control the pattern generator sothat while one channel of the pattern generator is selected to outputthe test pattern, the operation of the other channel of the patterngenerator is controlled.

As a result, a test pattern generator to be used in a bit errormeasurement is established which has M channels pattern generator whereeach of the channels selectively outputs the test pattern.

In case where the channel M is 2, the pattern generation controller 10,which selects the pattern generator in real time, includes a programcounter (PGC) 12 which repeatedly generates a frame period 12_(pset). Inreceiving frame period data 12_(dat) from the PGC counter 12, acoincidence detector 14 generates detection signal which is provide totwo state means (such as an SR flip-flop) which generates a selectsignal 16_(sel) for switching between time periods for multiplexing thetwo channels of the pattern generator. The pattern generation controller10 also includes a period counter 18 which provides the number of framesduring which the patterns will be repeatedly generated.

FIG. 2 is a block diagram showing a second solution by the firstinvention.

To solve the above noted problem, the configuration of the bit errormeasurement apparatus includes a pattern generator having M channels ofpattern generation corresponding to a received pattern signal 61 to betested which has the M selective patterns. The pattern generatorgenerates a select signal corresponding to each of the patterns in thereceived signal 61 to be tested. Each of the M channels of the patterngenerator is sequentially switched by this select signal and theselected pattern is provided to a comparator 65. When one channel of thetest pattern is output, the other channel of the test pattern iscontrolled by a pattern generation controller 10. A multiplexing meansis provided which receives the select signal from the pattern generationcontroller 10 and sequentially switches M channel output patterns fromthe pattern generator and provides the selected pattern to thecomparator 65. The bit error measurement apparatus further includes an Mchannel pattern synchronization part which detects synchronization ofpatterns for each channel when receiving the select signal from thepattern generation controller 10. When detecting that the patternscompared are not in the synchronization state, the M channel patternsynchronization part sends a clock mask signal to the correspondingpattern generator.

Therefore, the bit error measurement apparatus is established whichgenerates M channel selective patterns and provides the selectedpatterns to the comparator to be compared with the signal to be measuredand thus measures the bit errors in the received signal.

The bit error measurement system is thus established which has the abovenoted bit error pattern generator and the bit error measurementapparatus in which the M channel selective patterns are selectivelyprovided to the device to be tested by the bit error pattern generatorand the resultant output signal from the device under test is receivedand the bit error is measured by the bit error measurement apparatus.

As a more specific example, the pattern generator of the presentinvention preferably includes at least one channel of word patterngenerator or at least one channel of PRBS pattern generator. There aretwo pattern generation modes, one is a word generator 71_(word) whichgenerates a word pattern by reading the contents in a memory and a PRBSgeneration mode 71_(prbs) which generates a pseudo random pattern.

The bit error measurement system which is able to specify the positionof the pattern which caused the bit error functions as follows:

(1) When M=2, the pattern generation controller 10 in the bit errorpattern generator 20 controls to alternately switch two patterngenerators in real time. Both of the PRBS pattern generator and the wordpattern generator generate the pattern while only one of them beingselected to output the pattern. Alternatively, while one patterngenerator is generating the pattern, the other pattern generator'soperation is suspended.

(2) Similarly, the pattern generation controller 10 in the bit errormeasurement apparatus controls to provide the test patterns to thecomparator 65.

(3) The reference pattern generator 34 generates the patterns for thecomparison which are the same as the patterns generated by the testpattern generators in the bit error test pattern generator 20. Byreceiving each clock mask signal from the word pattern synchronizationpart 31 and the PRBS pattern synchronization part 32, test patterns aregenerated which are in synchronism with the received signal 61 when theapparatus is in the synchronization state.

(4) The word pattern synchronization part 31 receives the select signal16_(sel) from the pattern generation controller 10, and determineswhether the patterns are in the synchronization state in a period T_(oh)for generating a word pattern. If the error rate is greater than apredetermined value, the word pattern synchronization part provides aclock mask signal 31_(inh) to the word pattern generator 62_(word) so asto bring the word pattern into the synchronization state.

(5) Similarly, the PRBS pattern synchronization part 32 receives theselect signal 16_(sel) from the pattern generation controller 10, anddetermines whether the patterns are in the synchronization state in aperiod T_(payload) for generating a PRBS pattern. If the error rate isgreater than a predetermined value, the word pattern synchronizationpart provides a clock mask signal 32_(inh) to the PRBS pattern generator62_(prbs) so as to bring the word pattern into the synchronizationstate. Namely, both of the pattern synchronization parts are able toseparately, i.e., independently between the word pattern and the PRBSpattern, synchronize the pattern.

The solution of the problems in accordance with the second invention isshown in the following:

This invention relates to a bit error measurement system which includesa bit error pattern generator which is able to automatically switchclock edges of the clock signals to sequentially multiplex parallelpatterns to form a high speed test pattern.

FIG. 8 is a circuit diagram showing the second invention.

To solve the above noted problems, the error bit test pattern generatorof the present invention includes a clock frequency difference detector150 which measures the frequency of an input clock 111 and compares themeasured frequency with a frequency value at the time of the previousphase switch to detect whether the frequency change exceeds apredetermined frequency difference. By this detection signal, it isdetermined whether the apparatus is in the measurement state or theadjustment state and controls either to allow or prohibit the phaseswitch operation of a clock switch circuit 128.

Accordingly, a wide range pulse pattern generator is realized in whichparallel patterns generated by a pattern generator 113 are sequentiallymultiplexed to generate a high speed pattern. The pulse patterngenerator has an approach detection circuit 131 and a clock switchcircuit 128 and an intermediate retiming circuit 127 for canceling thedelay times ((τ₀ +τ₁ +,,+τ_(m-1)) in the multiplexing circuits in theprior stages of the intermediate retiming circuit 127 by automaticallychanging the clock edges. The wide range pulse pattern generator of thepresent invention avoids the unstable operation in the measurement stateof the bit error measurement system.

In the frequency difference detector 150, means for measuring afrequency f_(clk) is provided for comparing the frequency f_(clk) and aprevious frequency 156_(old). The frequency difference detector 150further includes means for prohibiting and allowing the switchingoperation of the clock switch circuit 128. If the detected frequencydifference is greater than a predetermined value, it is determined thatthe measurement system is in the adjustment state and thus allows theclock switch circuit 128 its automatic switching operation. In contrast,when the frequency difference is smaller than the predetermined value,it is deemed that the system is in the measurement state and thusprohibits the clock switch circuit 128 its automatic switchingoperation. The frequency difference detector 150 also includes means forholding the frequency value 156_(old) which is a frequency when theclock phase is automatically switched to other clock phase.

As a specific example, the frequency difference detector 150, as shownin FIG. 9, is formed of a reference gate time generator 152, a pulser153, a frequency counter 154, a count value latch register 156, asubtractor 158, a comparator 159, flip-flops 160, 161, an exclusive NOR(EXNOR) gate 162 and an AND gate 163.

The clock frequency difference detector 150 counts the frequency of theinput clock 111 and compares the counted value with the previousfrequency value. If the present frequency is greater than the previousfrequency by a predetermined value, the frequency difference detector150 allows/prohibits the clock switch circuit 128 its clock phaseswitching operation.

By an AND gate 170 and the frequency difference detector 150, it isdetermined whether the system is in the adjustment state or themeasurement state. If the system is in the measurement state, the clockswitching operation of the clock switch circuit 128 is prohibited.Therefore, the unstable operation of the clock switch circuit 128 duringthe measurement state is eliminated.

The solution of the problems by the third invention is shown in thefollowing:

This invention relates to a bit error measurement apparatus which iscapable of specifying a position of the test pattern which has beeninvolved in the bit error.

FIG. 12 is a block diagram showing a first embodiment of the thirdinvention.

To solve the problem, the invention of FIG. 12 includes a patternposition recording part 210 which stores the information regarding theposition of the reference pattern generation of a reference patterngenerator 262 in a memory 220 when a comparator 265 sends a errordetection signal 265_(a).

The bit error measurement apparatus, in addition to the pattern positionrecording part 210, the reference pattern generator 262 and thecomparator 265, further includes a pattern synchronization part 266, anerror counter 270 to specify the position of reference pattern generator262 which corresponds to the error in the input signal 261 to bemeasured.

FIG. 15 is a block diagram showing a second embodiment of the thirdinvention.

To solve the problem, the invention of FIG. 15 includes a patternposition recording part 230 which stores the information regarding theposition of the reference pattern generation of the reference patterngenerator 262 in a memory 220 when it received either one of N bit errordetection signals 265_(b) from a comparator 265. The memory 220 storesboth the reference pattern position information and the error detectionsignal 265_(b).

By this arrangement, when measuring the bit error of the input signal261 to be measured in a N bit parallel form, the position of the errorproduced in the input signal 261 can be specified as a pattern positionin the reference pattern generator 262.

The reference pattern generator is either a word pattern generator or aPRBS pattern generator. Alternatively, the pattern generator includesboth the word pattern generator and the PRBS pattern generator.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a bit error test pattern generatoraccording to the first invention.

FIG. 2 is a block diagram showing a structure of a bit error ratemeasurement apparatus for a received signal in accordance with the firstinvention.

FIG. 3 is a schematic diagram showing a frame structure of SDH (STM-1)which is an example of communication frame concerning the firstinvention.

FIG. 4 is a timing chart showing a select signal for multiplexing withinone frame period in accordance with the first invention.

FIG. 5 shows an example of a test arrangement for a bit errormeasurement system.

FIG. 6 is a block diagram showing a structure of a conventional biterror test pattern generator concerning the first invention.

FIG. 7 is a block diagram showing a structure of a conventional biterror measurement apparatus for a received signal concerning the firstinvention.

FIG. 8 is a block diagram showing a structure of a wide band pulsepattern generator of the second invention.

FIG. 9 is a block diagram showing an internal structure of a clockfrequency difference detector 150 of the second invention.

FIG. 10 is a timing chart showing operation timings of the clockfrequency difference detector 150 of the second invention.

FIG. 11 is a block diagram showing a conventional wide band pulsepattern generator concerning the second invention.

FIG. 12 is a block diagram showing an example of a structure of a biterror measurement apparatus used for a serial process.

FIG. 13(a) is a block diagram showing a structure of a pattern positionrecording part 210 corresponding to the serial process of a word patterngenerator according to the third invention.

FIG. 13(b) is a block diagram showing a structure of a pattern positionrecording part 210 corresponding to the serial process of a PRBS patterngenerator according to the third invention.

FIG. 14 is a histogram showing error distribution concerning the thirdinvention.

FIG. 15 is a block diagram showing an example of a structure of a biterror measurement apparatus according to the third invention used for aparallel process.

FIG. 16(a) is a block diagram showing a structure of a pattern positionrecording part 230 corresponding to the parallel process of the wordpattern generator according to the third invention.

FIG. 16(b) is a block diagram showing a structure of a pattern positionrecording part 230 corresponding to the parallel process of the PRBSpattern generator according to the third invention.

FIG. 17 shows an example of a test arrangement for using a bit errormeasurement system concerning the third invention.

FIG. 18(a) is a block diagram showing an example of a conventional biterror measurement apparatus concerning the third invention.

FIG. 18(b) is a block diagram showing an example of a conventional biterror measurement apparatus used in a parallel process concerning thethird invention.

FIG. 19 is a diagram showing relationship between a DEMUX 264_(a) and areference pattern signal 262_(a) concerning the third invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The embodiment of the first invention will be explained in thefollowing.

Namely, a bit error test pattern generator/bit error measurementapparatus is described below in which a test pattern is generated byinterchanging in real time a specific pattern and a random pattern anderrors are analyzed in the output signal from a device under test.

In this embodiment, test patterns are generated by switching in realtime a PRBS pattern generator which generates a long period randompattern and a word pattern generator which generates a specified bitsequence. Pattern synchronization is established for the patternsgenerated by the pattern generators as above and bit errors aremeasured. This embodiment is further explained with respect to anexample of a SDH (synchronous digital hierarchy) frame structure.

As shown in the SDH frame structure of FIG. 3, one frame is formed of 9lines with 270 byte length. First nine byte out of 270 bite length is anoverhead (OH) and the remaining 261 byte is a payload. It is assumed inthe following that, test patterns for testing this frame structure, itis necessary to provide a known test pattern for the position of theoverhead and a random pattern for the position of the payload. A testpattern generator generates the frame pattern by repeating N frameperiods. Namely, for every frame period, the same bit stream isgenerated for the overhead while the random bit stream is generated forthe payload.

For generating this type of test patterns, a bit error test patterngenerator of the present invention includes a pattern generationcontroller 10 as shown in FIG. 1 in addition to the conventionalstructural components. A PRBS generator 62_(prbs), a word generator62_(word), a multiplexer (MUX) 62_(m), and a buffer amplifier 62_(buf)are basically the same as that in the conventional technology. However,each of the PRBS generator 62_(prbs) and the word generator 62_(word)has a function of suspending the pattern generation.

The pattern generation controller 10 is formed of a program counter 12,a coincidence comparator 14, a set-reset flip-flop (SRFF) 16, and aperiod counter 18.

The program counter 12 is a counter for down counting by repeatedlypresetting the frame period 12_(pset) for every borrow signal 12_(bor).The program counter 12 generates predetermined frame period data12_(dat) by counting a clock signal 72. The frame period 12_(pset) isset by an external CPU to meet with desired frame periods.

The set reset flip-flop (SRFF) 16 produces a select signal as shown inFIG. 4 which switches two pattern generators in a frame period. Whenreceiving the frame period data 12_(dat) from the program counter 12,the coincidence comparator 14 detects time data for the 9 byte of theoverhead OH and changes the set reset flip-flop 16 to a set state.

When receiving the borrow signal 12_(bor) from the program counter 12,the set reset flip-flop 16 is changed to a reset state. The selectsignal 16_(sel) thus produced at the output of the flip-flop is providedto the multiplexer 62_(m). The input patterns are multiplexed in realtime by the multiplexer 62_(m) and are provided to the buffer amplifier71_(buf). The select signal is also provided to the PRBS generator62_(prbs) and an address counter 62_(ctr) in the word generator62_(word) to alternately suspend the pattern generation in thegenerators.

In this manner, the pattern generator selected by the multiplexer 62_(m)operates while the other pattern generator is in a temporarily waitingstate. By alternately repeating this process, the test pattern which isa multiplex of both of the patterns is generated by the patterngenerator.

The period counter 18 is to repeat the overhead period for N frametimes. The period counter 18 receives the borrow signal 12_(bor) fromthe program counter 12 to count down the contents. By a borrow signal18_(1d) from the counter 18 is provided to a load input of the addresscounter 62_(ctr) to set the counter 62_(ctr) to an initial value. Theperiod counter 18 repeats this process by setting itself to an initialvalue 9×N by the borrow signal 18_(1d). Here, the initial values or thevalue applied to the coincidence comparator 14 are freely set by theexternal CPU to form a desired interval of the N frames.

In the following, the bit error measurement apparatus 30 for measuringthe received signal 61 which is derived through the device under testwhen given the test pattern from the above noted test pattern generator20.

As shown in FIG. 2, the measurement apparatus includes two separatepattern synchronization parts, i.e., a word pattern synchronization part31 and a PRBS pattern synchronization part 32, and a reference patterngenerator 34 which is a multiplexing type pattern generator as in thetest pattern generator 20.

Similar to the bit error test pattern generator 20, a pattern generationcontroller 10 in the reference pattern generator 34 controls to generatea multiplexed pattern signal 34_(pat) which is provided to one inputterminal of a comparator 65.

The difference in the reference pattern generator from that of the testpattern generator 20 is that, to synchronize with the received signal61, the word pattern synchronization part 31 and the PRBS patternsynchronization part 32 separately include a clock suspension function(pause function) to suspend the pattern generation for every one clocktime. Although the clock suspension function is the same as that in theconventional technology, each of the synchronization parts has anindependent suspension function in this invention.

The detections of the pattern synchronization are performed separatelyand in parallel in the two pattern synchronization parts. When the biterror rates in the both paths are lower than a predetermined value, themeasurement system is shift to a real bit error measurement state toactually measures the bit error of the received signal.

One synchronization detection path includes the word patternsynchronization part 31. The word pattern repeats for every N frames.The operation of detecting a synchronization position is different fromthat of the conventional one in that it operates only in the worddetection period T_(OH). Namely, a synchronization detection counter66_(a) is enabled only during the high level range of the select signal16_(sel) from the pattern generation controller 10. As in theconventional technology, when the error rate is higher than apredetermined value, a clock mask signal 31_(inh) is provided to theword pattern generator 62_(word) to shift the pattern generation by oneclock period. When the error rate reaches the predetermined value, it isdeemed that the word pattern reaches the synchronization state and thesynchronization detection operation is suspended. Thus, the word patternsynchronization part generates a synchronization detection signal31_(sync).

The other synchronization detection path includes the PRBS patternsynchronization part 31. Similar to the description above, the operationof detecting a synchronization position is performed only during the lowlevel range of the select signal 16_(sel) from the pattern generationcontroller 10. When the error rate is higher than a predetermined value,a clock mask signal 32_(inh) is provided to the PRBS pattern generator62_(prbs) to shift the pattern generation by one clock period. When theerror rate reaches the predetermined value, it is deemed that the PRBSpattern reaches the synchronization state and the synchronizationdetection operation is suspended, and as a result, a synchronizationdetection signal 32_(sync) is generated.

After reaching the synchronization states in both of the patterngenerators, the system moves to the measurement state to measure a biterror.

As proceeding the foregoing, specified pattern sequence and the longrandom period pattern are multiplexed to realize a bit error measurementsystem which is applicable to any desired communication frame structure.It is apparent that the present invention is also applicable to theconventional way of measurement wherein either the word pattern or thePRBS is selected to be output.

Other embodiments of the first invention are shown in the following.

In the foregoing description, the word pattern or the PRBS pattern areone bit pattern generator. However, each of the pattern generators maybe formed of M bit parallel pattern generators wherein the outputs areparallel-serial (M-to-1) converted by a multiplexer to form a serial bitstream.

Further, in the foregoing embodiment, the comparator 65 compares thepattern for one bit. However, it is also possible to compare for theunit of M bits by the comparator 65 by including a demultiplexes whichserial-parallel (1-to-M) converts the patterns.

Further, in the foregoing embodiment, the test pattern generator is acombination of the word pattern generator and the PRBS patterngenerator. However, it is also possible to combine two word patterngenerators or two PRBS pattern generators to multiply two specific wordpatterns or two random patterns.

Furthermore, in the foregoing embodiment, the test pattern generatorincludes two pattern generators to multiply the patterns therefrom.However, it is also possible to include P (P is more than 2) patterngenerators while the surrounding circuits such as patternsynchronization parts are arranged to meet the number of patterngenerators.

The embodiment in accordance with the second invention is shown in thefollowing:

This invention relates to a bit error measurement system which includesa bit error pattern generator which is able to automatically switchclock edges of the clock signal to sequentially multiply parallelpatterns to form a high speed test pattern.

An example of the embodiment of the present invention includes afunction to automatically inhibit the operation in a clock switchcircuit 128 by detecting the frequency change in an input clock 111.

As shown in FIG. 8, the structure of a wide band pulse pattern generatoradditionally includes a clock frequency difference detector 150 and anAND gate 170 to the conventional structure.

The AND gate 170 is connected between the output of a comparator 134 anda clock input of a T flip-flop 135 to prohibit the operation of theT-type flip-flop 135. The clock frequency difference detector 150receives an intermediate speed clock signal 150_(in) which is a clocksignal produced by dividing the input clock to detect the frequencychanges. The output signal of the clock frequency difference detector150, i.e., a phase switch enable signal 160_(enb), is provided to oneinput terminal of the AND gate 170 to either allow or prohibit the phaseswitch operation.

This control operation is explained with reference to an internalstructure of the clock frequency difference detector 150 in FIG. 9 and atiming chart of FIG. 10.

The frequency difference detector 150 measures a frequency of the inputclock 111 for every fixed time period, and compares the measured datawith the original frequency value. If the frequency change is greaterthan a predetermined value, the phase switch enable signal 160_(enb) isgenerated to enable the switch operation of the clock switch circuit128. The clock frequency difference detector 150 is formed of areference gate time generator 152, a pulser 153, a frequency counter154, a count value latch register 156, a subtractor 158, a comparator159, flip-flops 160, 161, an exclusive NOR (EXNOR) gate 162 and an ANDgate 163.

The reference gate time generator 152 is a 16 bit divider to provide areference gate time to the frequency counter 154 as a count time. Thereference gate time generator 152 receives a reference clock 151 (10 MHZfor example) and divides the reference clock 151 by a predetermineddivision rate 152_(div) to repeatedly produce a divided time signal152_(gate). The divided time signal 152_(gate) is provided to an enableterminal of the frequency counter 154 and the pulser 153. Here, thedivision rate 152_(div) is set freely by the CPU (computer) which isdetermined such that the 16 bit divider will not overflow in response tothe frequency of the intermediate clock signal 150_(in) and the countvalue will satisfy the desired resolution (0.2% for example).

The pulser 153 is to form a pulse signal 153_(pls) based on the dividedtime signal 152_(gate). The pulse signal 153_(pls) is provided to areset input of the frequency counter 154, clock inputs of the flip-flops160 and 161, and one input terminal of the AND gate 163.

The frequency counter 154 is a counter for counting the intermediatespeed clock signal 150_(in). When receiving the pulse signal 153_(pls),the frequency counter 154 resets to an initial value 0, then counts thenumber of clocks of the intermediate speed clock signal 152_(in) duringthe high level period of the divided time signal 152_(gate). During theperiod when the divided time signal 152_(gate) is in the low level, thecounted value 152_(cnt) is maintained and is supplied to one input ofthe subtractor 158 and to the count value latch register 156.

The subtractor 158 subtracts the previous frequency value 156_(old) heldin the count value latch register 156 from the count value 152_(cnt)from the frequency counter 154. The resultant subtracted value 158_(sub)is supplied to one input of the comparator 159.

The comparator 159 compares the subtracted value 158_(sub) and acomparison value 157_(cmp), and if the subtracted value 158_(sub) isgreater than the comparison value 157_(cmp), the comparator 159 providesa high level signal to an input of the flip-flop 160. The comparisonvalue 157_(cmp) is a value freely set by the CPU, and is set in advance,for example, to a value which is 2-5% different from the intermediatespeed clock signal 150_(in).

The flip-flop 160 latches the output signal of the comparator 159 andoutputs a phase switch enable signal 160_(enb) to one input of the ANDgate 170 so as to inhibit the operation of the clock switch circuit 128.When the phase switch enable signal is in the high level, the system isin the adjustment state and thus operation of the clock switch circuit128 is allowed. When the phase enable signal is in the low level, thesystem is in the measurement state, and thus the operation of the clockswitch circuit 128 is prohibited.

To renew the count value latch register 156, a load pulse signal156_(1d) is produced by the flip-flop 161, the exclusive OR gate 162 andthe AND gate 163. More particularly, the flip-flop 161 shifts the signalfrom the flip-flop 160 to hold the phase switch enable signal 160_(enb)of the previous cycle. Both of the phase switch enable signals are inputto the exclusive OR gate 162 so as to determine whether there is anychange between the present and previous signals. The output of theexclusive OR gate 162 is provided to the count value latch register 156through the AND gate 163. Thus, the count value 154_(cnt) is renewed andheld in the count value latch register 156 as data for the nextcomparison.

As in the foregoing, by setting the division value 152_(div) and thecomparison value 152_(cmp) to appropriate values, when the rate offrequency change of the input clock 111 is detected to be smaller thanthe predetermined value (for example, 2-5% frequency ratio), the switchoperation of the clock switch circuit 128 is automatically enjoined. Asa consequence, a stable wide band pulse pattern generator isaccomplished by effectively preventing the unstable operation in themeasurement state.

Other embodiments of the second invention are shown in the following.

In the foregoing explanation of the embodiment, the input clock signalfor the clock frequency difference detector 150 is obtained by thedivided clock taken from a 1/2 divider circuit 112_(n-m) as theintermediate speed clock signal 150_(in). Since it is only necessary tocount the input clock 111, it is also possible to directly count theinput clock 111. Alternatively, to receive the clock signal from theother 1/2 divider by setting the division value 152_(div) accordingly.

In the foregoing explanation of the embodiment, the internal structureof the clock frequency difference detector 150 is formed of the abovedescribed components, it is also possible to use other circuit structureand components to establish the equivalent circuit of the clockfrequency difference detector.

Further, it may be preferable to provide an indicator on a display panelto show the state of the phase enable switch signal 160_(enb) whichshows the output state of the flip-flop 160.

In the foregoing explanation of the embodiment, the control of thepermission/prohibition of the switching operation of the clock switchcircuit 128 is carried out solely by the clock frequency differencedetector 150. However, in addition to this function, an additionalcontrol function such as a manual input is also possible to forciblypermit/prohibit the operation of the clock switch circuit 128.

An embodiment in accordance with the third invention is described in thefollowing.

As explained below, this embodiment relates to a bit error measurementsystem which specifies and records the position of test patterns whichcaused a bit error.

First, the explanation of the invention for the serial process is givenin the following:

This embodiment of the invention is an example which processes in a unitof one bit. This example is added with a memory function which storesthe address information of the reference pattern generator at the timewhen the bit error is produced.

The configuration of the measurement system is, as shown in FIG. 12, apattern position recording part 210 is added to the conventionalconfiguration.

The reference pattern generator 262 includes two kinds of patterngenerators based on the requirement of pattern generation modes. One isa word pattern generator 251 using a memory and the other is a PRBSpattern generator 252 for generating pseudo random patterns.

FIG. 13(a) is a block diagram showing a structure of the patternposition recording part 210 corresponding to the word pattern generator251. The pattern position recording part 210 has a gate 212, an addresscounter 222 and a memory 220.

In the case of using the word pattern generator 251, the addressinformation is a address signal 251_(adr) itself for the word patterngenerator 251. This address signal 251_(adr) (for example, 18 bitlength) is provided to a data input of the memory 220.

In receiving a bit error signal 265_(a) from the comparator 265, theerror signal is formatted to a pulsed signal by a clock 260 at the gate212 and is provided to a write enable input of the memory 220. As aconsequence, for every bit error, the address information of the patternposition in the word pattern generator 251 is stored in the memory 220.

After acquiring the address information, the CPU reads the contents inthe memory 220 and displays address caused the bit errors in variousdisplay modes. For example, the error distribution for every fixedaddress interval is shown in a histogram form of FIG. 14 so that theerror analysis, such as to determine as to which position of thereference pattern 262_(a) has caused the error, is easily carried out.

FIG. 13(b) is a block diagram showing a structure of the patternposition recording part 210 corresponding to the PRBS pattern generator252. The pattern position recording part 210 has a gate 212, a shiftregister 218, an address counter 222 and a memory 220.

In the case of using the PRBS pattern generator 252, one bit is notenough to show the information of the pattern position of the referencepattern. Thus, in receiving a bit stream 265_(prbs) of the PRBS patternsequence, the bit stream is converted to n bit parallel data which isdeemed to be address information and is provided to a data input of thememory 220. The length of the address information in this case needs alength corresponding to the number of stages in the PRBS. For example,in case where the PRBS has 31 maximum stages, the parallel bit length ofthe address information must be n=31.

Therefore, in receiving a bit stream 265_(prbs) of the PRBS patternsequence, the shift register 218 converts the bit stream to 31 bitparallel data. This parallel information is provided to the data inputof the memory 220. The remaining operation of the pattern positionrecording part 210 is the same as described with respect to that of theword pattern generator 251.

Next, the explanation of the invention for the parallel process is givenin the following:

FIG. 15 shows a structure of the bit error measurement apparatus for theparallel process when N=16 bits. In this case, the signal 261 to bemeasured which is an ultra high speed signal is converted to a low speedparallel signal before the measurement of the bit error rate. Theprinciple of operation is the same as that of the serial process. Inthis configuration, a demultiplexes 264 and a divider 263 are added tothe configuration of the above noted serial process.

As shown in FIG. 16(a), a pattern position recording part 230 for theword pattern generator 251 is basically the same as explained in theabove with respect to the serial process. Therefore, if an OR gate 215detects an error in any bit out of the parallel 16 bits of the bit errordetection signal 265_(b), a gate 212 produces a write enable pulse. Adivided clock 263_(a) is a clock produced by dividing the clock 260. Thebit error detection signal 265_(b) which is a 16 bit parallel signal isdirectly provided to a data input of a memory 220. Also, the addresssignal 251_(adr) of the word pattern generator 251 is provided to a datainput of the memory 220. Thus, both data are stored in the memory 220.The other operations are the same as that of the serial process.

As shown in FIG. 16(b), when the pattern generator is the PRBS patterngenerator 252, a pattern position recording part 230 needs to store thePRBS address 218_(adr) which is the maximum address length, i.e., n=31bits, for example, in the memory 220. Thus, the pattern positionrecording part 230 includes a shift register 218. Other operations arethe same as in the serial process.

Industrial Applicability

Since the present invention is configured as in the foregoing, it hasthe following effects:

The effects of the first invention is as follows:

This invention includes the bit error test pattern generator/bit errormeasurement apparatus which is able to switch between specific patternsand random patterns in real time and analyze the bit errors in theoutput signal from the device under test.

The pattern generation controller 10 in the bit error test patterngenerator 20 controls to alternately switch the two pattern generatorsin real time. The pattern generator which is not outputting the patternis in the standby state in temporarily waiting for the next patterngeneration. As a result, the invention accomplishes to generate themultiplexed patterns.

The reference pattern generator 34 generates the patterns for thecomparison which are the expected patterns and are the same as thepatterns generated by the pattern generators in the bit error testpattern generator 20. By receiving each clock mask signal from the wordpattern synchronization part 31 and the PRBS pattern synchronizationpart 32, test patterns are generated which are in synchronism with thereceived signal 61 when the apparatus is in the synchronization state.

The word pattern synchronization part 31 receives the select signal16_(sel) from the pattern generation controller 10, and determineswhether the patterns are in the synchronization state in a period T_(oh)for generating a word pattern. If the error rate is greater than apredetermined value, the word pattern synchronization part provides aclock mask signal 31_(inh) to the word pattern generator 62_(word) so asto bring the word pattern generator into the synchronization state.

Similarly, the PRBS pattern synchronization part 32 receives the selectsignal 16_(sel) from the pattern generation controller 10, anddetermines whether the patterns are in the synchronization state in aperiod T_(payload) for generating a PRBS pattern. If the error rate isgreater than a predetermined value, the word pattern synchronizationpart 32 provides a clock mask signal 32_(inh) to the PRBS patterngenerator 62_(prbs) so as to bring the PRBS pattern generator into thesynchronization state. Namely, both of the pattern synchronization partsare able to separately, i.e., independently between the word pattern andthe PRBS pattern, synchronize the patterns.

Accordingly, the bit error measurement system is achieved which is ableto sequentially multiplex the parallel patterns and measure the biterrors corresponding to the multiplexed patterns.

The effects of second invention is as follows:

This invention relates to the bit error measurement system whichincludes a bit error pattern generator which is able to automaticallyswitch clock edges of the clock signals to sequentially multiplexparallel patterns to form a high speed test pattern.

The AND gate 170 controls the operation of the T-type flip-flop 135 whenreceiving the phase switch enable signal 160enb from the clock frequencydifference detector 150.

The clock frequency difference detector 150 counts the frequency of theinput clock 111 and compares the counted value with the previousfrequency value. If the present frequency is greater than the previousfrequency by a predetermined value, the frequency difference detector150 allows/prohibits the clock switch circuit 128 its clock phaseswitching operation.

By this arrangement, it is determined whether the bit error measurementsystem is in the adjustment state or the measurement state. If thesystem is in the measurement state, the clock switching operation of theclock switch circuit 128 is prohibited. Therefore, the unstableoperation of the clock switch circuit 128 during the measurement stateis eliminated and thus, the stable, wide band pulse pattern generator isachieved.

The effects of the third invention is as follows:

This invention relates to a bit error measurement apparatus which iscapable of specifying and recording a position of the test pattern whichcaused the bit error.

The pattern position recording part 210 stores the information regardingthe reference pattern generation of the reference pattern generator inthe memory 220 when the comparator sends the error detection signal265a. The information regarding the reference pattern position is theaddress of the word pattern generator when the word pattern generator251 is used. In contrast, when using the PRBS pattern generator 252, theinformation regarding the reference pattern position is the n bitparallel data which has been converted from the bit stream 265_(prbs) ofthe PRBS pattern.

The pattern position recording part 230 stores the information regardingthe reference pattern generation of the reference pattern generator andas well as the N bit parallel error detection signals 265_(b) in thememory so that the information on which position of the error in the Nbit can be specified.

In this arrangement, according to the present invention, the position ofthe reference pattern 262_(a) which caused the error can be specified,which further facilitates the bit error analysis.

What is claimed is:
 1. A test pattern generator to be used for a biterror measurement and has a M channel selectable pattern generator togenerate selected test patterns, characterized in that said test patterngenerator having:a pattern generator having M channels for patterngeneration: and a pattern generation controller (10) for controlling thepattern generation by sequentially switching each of said channels ofsaid pattern generator in real time such that while one channel of saidpattern generator is selected and generating the test pattern, the otherchannels are waiting for the next pattern generation.
 2. A test patterngenerator as defined in claim 1, wherein said pattern generator has twochannels and said pattern generation controller (10) is characterized inhaving that:a program counter (12) for repeatedly generating a frameperiod (12_(pset)) two level means for generating a select signal(16_(sel)) which defines selection time periods of said two channels ofsaid pattern generator through a coincidence comparator (14) whichreceives frame period data (12_(dat)) from said program counter (12);and a period counter (18) for providing a number of said frame periodrepeatedly generated.
 3. A bit error measurement system to measure a biterror of a device and has a M channel selectable pattern generator toprovide the selected test patterns to a device under test and receivethe resultant signals from the device under test to measure a bit error,characterized in that said test pattern generator having:a patterngenerator having M selectable channels for pattern generationcorresponding to a test pattern received signal (61); a patterngeneration controller (10) for controlling the pattern generation bysequentially generating a pattern generation period signal for switchingeach of said channels of said pattern generator such that while onechannel of said pattern generator to be provided to a comparator (65) isselected and generating the test patter, the other channels are waitingfor the next pattern generation; switching means for selectivelyswitching reference patterns of a reference pattern generator having Mchannels of pattern generation when receiving a select signal from apattern generation controller (10) to provide said reference patterns tosaid comparator (65); and M channel pattern synchronization parts eachof which separately detects a synchronization of said pattern andprovides a clock mask signal to a corresponding pattern generator whensaid pattern is not in said synchronization.
 4. A bit error measurementsystem as defined in claims 1 or 3, wherein said M channels of saidpattern generator include at least one word pattern generator and atleast one PRBS (pseudo random binary sequence) pattern generator.
 5. Abit error measurement system as defined in claims 1 or 3, wherein saidword pattern generator (62_(word)) generates word patterns by readingout contents in a memory.
 6. A bit error measurement system as definedin claims 1 or 3, wherein said PRBS (pseudo random binary sequence)pattern generator (62_(word)) generates pseudo random patterns.
 7. A biterror measurement system characterized in having that:a wide bandpattern generation circuit for sequentially multiplexing parallelpatterns generated by a pattern generator circuit (113) to form a highspeed pattern, said wide band pattern generation circuit having anapproach detection circuit (131), a clock switch circuit (128), anintermediate retiming circuit (127) and a clock edge switch circuitwhich cancels delay times (τ₀ +τ₁ +,,+τ_(m-1)) in said intermediateretiming circuit; and a clock frequency difference detector (150)provided in said wide band pattern generation circuit for counting afrequency of an input clock (111) to detect whether the countedfrequency exceeds a predetermined difference from the frequency at aprevious phase switching to determine either permit or prohibit a phaseswitch operation in said clock switch circuit (128).
 8. A bit errormeasurement system as defined in claim 7, wherein said clock frequencydifference detector (150) includes:means for counting a frequency(f_(clk)) of an input clock to be used for multiplexing said patterns;means for permitting an automatic switching operation of said clockswitch circuit (128), by judging that the bit error measurement systemis in a adjustment state, when detecting a frequency difference which isgreater than a predetermined value by comparing said frequency (f_(clk))and a previously measured frequency (156_(old)), and for prohibitingsaid automatic switching operation of said clock switch circuit (128),by judging that the bit error measurement system is in a measurementstate, when said frequency difference is smaller than said predeterminedvalue; and means for holding said previously measured frequency(156_(old)) taken at a time when said automatic switching operation istaken place.
 9. A bit error measurement system having a referencepattern generator (262), a comparator (265), a pattern synchronizationpart (266) and an error counter (270) for measuring bit errors of asignal (261) under test characterized in that:said bit error measurementsystem has a pattern position recording part which stores addressinformation of said reference pattern generator (262) in memory meanswhen receiving an error detection signal (265_(a)) from said comparator(265).
 10. A bit error measurement system having a reference patterngenerator (262), a comparator (265), a pattern synchronization part(266) and an error counter (270) for measuring bit errors of a signal(261) under test for every N bit parallel characterized in that:said biterror measurement system has a pattern position recording part whichstores address information of said reference pattern generator (262)when receiving an error signal in any one of N bit error detectionsignals (265_(a)) from said comparator (265) and said N bit errordetection signals (265_(a)) in memory means.
 11. A bit error measurementsystem as defined in claims 9 or 10, wherein said reference patterngenerator is either a word pattern generator or a PRBS pattern generatoror a combination of both of said pattern generators.